A pervasive trend in modern integrated circuit manufacture is to increase the amount of data stored per unit area on an integrated circuit memory unit, such as a flash memory unit. Memory units often include a relatively large number of core memory devices (sometimes referred to as core memory cells). For instance, a conventional dual cell memory device, such as a charge trapping dielectric flash memory device, is capable of storing two bits of data in a double-bit arrangement. That is, one bit can be stored using a first charge storing region on a first side of the memory device and a second bit can be stored using a second charge storing region on a second side of the memory device.
In a conventional charge trapping dielectric memory device, the charge storing regions are part of a non-conductive charge trapping layer, which is disposed between a relatively thick (e.g., about 100 angstroms) bottom (or tunnel) dielectric layer and a relatively thick (e.g., about 100 angstroms) top dielectric layer. These dielectric layers can be formed over a P-type conductivity silicon substrate having a series of bitlines disposed therein. A series of conductive wordlines, often made from polycrystalline silicon, can be formed over the dielectric layers to serve as gate electrodes for each memory device. The core memory devices can be addressed by applying appropriate voltages to the wordlines and/or the bitlines.
During programming and reading of the core memory devices, the bitlines can function as sources (i.e., a source of electrons or holes) and drains with an active channel region defined therebetween. Programming of such a memory device can be accomplished, for example, by hot electron injection. Hot electron injection involves applying appropriate voltage potentials to each of the gate electrode (e.g., about 9 Volts to about 11 Volts), the source, and the drain of the memory device for a specified duration until the charge trapping layer accumulates charge.
Where possible, it is desirable to scale down memory devices, while still maintaining desirable qualities, such as adequate data retention, and optimized performance. However, memory device downscaling can result in a number of performance degrading effects. For example, in memory devices with an active channel region having a relatively short length, a memory device can experience a number of undesirable electrical characteristics referred to as short channel effects (SCE). SCE generally occur when the gate electrode does not have adequate control over the active channel region, and can include threshold voltage (VT) roll off, off current (Ioff) roll-up and drain induced barrier lowering (DIBL). As the physical dimensions of the device decrease, SCE can be become more severe.
In view of the foregoing, there is a need in the art for improved memory devices, such as charge trapping dielectric flash memory devices, which optimize scale and performance.